PCB Controlled Impedance - Phil's Lab #171

In this video, I'm going to show you an extract of one of the course lessons of my advanced digital hardware design course. This course overall teaches you how to design your own advanced digital hardware, including FPGA, system on chips, such as the AMD Xylink zinc we're using in this design, as well as certain peripherals such as DDR memory, gigabit Ethernet, and so on. The course covers the essentials of using these elements in your own hardware design. And with this particular free YouTube video, I'd like to show you an extract or part of lesson five where lesson five contains buildup, stack up, and controlled impedance information. And I'm showing you in this video just the controlled impedance section. If you'd like to support this channel and thank you for everyone who has already signed up to the course, you can sign up to the course with using the links in the description box below. I also have another mix signal keycat course. And with your support, this allows me to continue making free YouTube content. So, thank you very much for that. At the time of this video, I am also working on two new courses. One is an alim designer. I call it for now zero to hero. So teaching the fundamentals and basics of alim designer as well as some advanced topics but going through the entire project creation process all the way to generating the manufacturing files. And this is for USB 3. 0 to 1 GB Ethernet adapter. And the second course I'm working on is using analog devices, shark processors, digital signal processes. They're very powerful and very useful in certain applications. And in that second course, we will be going through a simple sharkbased guitar pedal, looking at the hardware design, but also how to bring up the processor and get audio running in and out, connecting peripherals with our firmware design using Crosscore embedded studio or CCS for short. I'll leave a link to this course survey in the description box below where you can register your interest and be notified via email once these courses go live. Again, thank you so much for your support and I hope you enjoy this sample lesson extract. After having looked at buildup and stackup, we are ready to move on to controlled impedance. Defining what this is, when we need this, and how to implement that in our own high-speed designs. First of all, let's talk about impedances and the maximum power transfer theorem. theorem tells us how the impedances need to be arranged and matched to deliver maximum power from a driver through a transmission line to a load. We can see the system here. We have a driver. This could be a typical output driver of maybe a bus signal. Then we have a trace which we indicate here as a transmission line which has some impedance. The driver has some sort of output impedance. The trace has an characteristic impedance. And then we send that along the trace towards a load which might be a receiver. If all these impedances are matched that means Z which is the characteristic impedance. If these are all the same with the driver transmission line and the load then we get maximum power transfer. Maximum power transfer can be very important for example for GPS signals or any RF signals or we want to make sure that our very low signal strength signal not reduced even further. If there are impedance mismatches for example if the driver impedance is not quite the transmission load impedance or the transmission line impedance isn't quite the load impedance and any combination of those. An impedance mismatch means a discontinuity and at those discontinuities or at that discontinuity that mismatch will create a reflection or various reflections. This is illustrated here. We have a driver again z a length of transmission line also at z impedance. Then we have this discontinuity which is higher or lower than zn and the magnitude is also of course important and for a certain length. Then a piece of transmission line also at Z N and a load at Z N. This impedance mismatch due to this maybe badly formed trace or element. This could be a component as well can create an impedance discontinuity which can create a reflection which could cause ringing which are signal integrity issues and that also lead to EMI issues. As we'll see this is even more critical the higher frequency signal we have. This can be very critical and is very critical in high-speed design as these impedance mismatches can cause problems that make your board not function or not pass EMC testing. This of course brings up several questions. The first is what determines the magnitude of the reflection? For example, how much of an impedance discontinuity in comparison for example to our characteristic impedance can we sustain? What length of the impedance discontinuity is okay and so on. In short, and we'll look at termination later on when we look at DDR3 memory, but for now, the maximum frequency of the signal is important in comparison to the length of the discontinuity. So, if we have a higher speed signal, a high frequency signal, a same length discontinuity for that higher speed signal will create worse reflections. Impedance discontinuities happen all the time in real world systems. There's never going to be a really ideal case. The question is then, how much of a mismatch is tolerable? For example, if we're going from a trace into a pad, there will be impedance mismatches due to different trace widths, pad widths, and so on. The question is, when is this even important? And again, we'll see more on reflections and calculating magnitudes of reflections in the DDR3

memory and termination section. But for now, we want to figure out when the length of this discontinuity plays a role in our system. The term or rule of thumb that's often used is named the critical length. The critical length known as LCR is when our trace or when a component starts to become as distributed element. Distributed element means the wavelength of a signal is comparable to the size of the component it's flowing through. Very simply speaking. So if a trace length is comparable to the wavelength of a signal, remember we're dealing with electromagnetic waves. Then we're approaching this critical length when the trace starts to become a distributed element. And this is when we need to start worrying about reflections, impedance mismatches and so on. There are many rules of thumb for the critical length, but I've taken this value, this 1 12th of a signal wavelength from Rick Hartley. The rule of thumb is that the critical length is a 12th of the signal wavelength in the dilectric material. In the dilectric material is important because the dilectric material will slow down our electromagnetic waves depending on the dilectric constant. The formula is shown here. The critical length is the speed of light C divided by the maximum frequency of the signal. For example, for a Wi-Fi signal, this might be 2. 4 GHz or 5 GHz. This C / F is then further divided by the square root of epsilon, which depends on the dilectric material and then divided by 112th because we're looking at a 12th of the signal wavelength in the dilectric material. We can see immediately that we can't change the speed of light. But what we can influence for example is the maximum frequency of the signal or what we have in the design is the maximum frequency of the signal and also our dialectric materials. So for example from the pre- prags the cause if it's an outer layer trace or an inner layer trace that will change the critical length. Now this formula is very straightforward for purely analog signals say sine waves as we can see on the right hand side. This is incredibly easy. We know C the speed of light. We typically know our dilectric constant. All we need to know is the maximum frequency of our analog signals. So for example, for an antenna trace on an outer layer for an L1 band GPS receiver, the maximum frequency is approximately 1. 6 GHz. Plugging in those values, the speed of light is about 3 * 10 8 m/s. Then we plug in the bottom our frequency in herz. For an out layer trace, this is the effective dilectric constant is about 3. 3 typically. But then we divide this whole number by 12 to get a 12th of a signal wavelength. From this we see that the critical length LC crit is then 8. 7 mm. Keep in mind though that often times we have to also include the lengths within for example a GPS receiver within a package within connectors and so on. So we're not just looking at traces or components and so forth. The question is once we have this value this for example 8. 7 mm in the case of an L1 GPS antenna trace, what does this mean? In this specific example, any trace or any element, for example, if we're rooting through a capacitor, resistor, and so on, any trace or element shorter than 8. 7 mm, shorter than the critical length, appears to the signal as a lumped element, and anything above 8. 7 mm appears to the signal as a distributed element. This means below the critical length, we can route the trace or our components in pretty much any manner. We can route them as wide or as narrow as you want. The impedance disc's continuity is comparatively short and thus insignificant. Again, remember the picture from one of the first two slides. This length of the impedance discontinuity almost no matter how large this impedance discontinuity is doesn't really matter if L is below the critical length. Problems start occurring. However, if we go above this critical length or close to this critical length, then we need to control the impedance of the trace. Meaning our Z discontinuity, this Z disc or our trace needs to be matched to the driver as well as to the load. Again, due to maximum power transfer and minimizing reflections. In any case, I'd highly recommend not routting the trace in any manner. In any case, I'd always recommend keeping traces as short as possible regardless if you're close to the critical length or not. I'd also recommend pretty much always impedance controlling traces for high-speed signals regardless of their length. Keeping traces as short as possible also helps with the skin effect, losses, cross talk and noise. For analog signals, finding the critical length and therefore then knowing when we need to impedance control and when not is pretty straightforward. We just plug in speed of light, dialectric constant and our maximum frequency in the analog signal. Analog signal again typically will be some sort of sine wave or sum of a few sine waves as we can see on the top right hand side. However, this course and in modern designs, we typically have to deal quite a lot with digital signals. Digital signals in comparison are not just a single sine wave. On the right hand side, a digital signal will be more like a square wave. And I've written non ideal square wave because an ideal square wave will have essentially vertical edges which is not

possible in real life. Therefore, the digital square waves will be somewhat trapezoidal. We'll start from a logic low. We'll ramp up in a certain time called the rise time on this rising edge. Then we'll stay at logic high and ramp down during this falling edge in the fall time back to logic zero. And then we can have trains and pulses of these trapezoidal waves. If we increase for example the edge rates so make these edges steeper as we can see in the bottom right hand picture this will change the characteristics of this square wave. Remember any wave is pretty much just a sum of sinosidal harmonics. Again, this is according to Fury. Not only do we have the edges, of course, but we typically have a period. So, for a clock, we have a pretty much defined period. But people typically often confuse that and say that the clock period is the highest frequency within a system. And this couldn't be further from the truth, as we'll see. The highfrequency content of a digital square wave, for example, a trapezoidal wave, is contained predominantly in the edges. So, these fast upward or downward sloping edges, not in the clock period. Therefore, if we have shorter rise and fall times, for example, the wave on the bottom right has a shorter rise and fall time than the wave in the middle. If we have shorter rise and fall times, that increases the highest maximum frequency content. Let's talk a bit more about rise and fall times, as these will be important to figuring out what our maximum frequency content is. It's also important first of all to note that there are different definitions for rise and fall times. This could be from 20 to 80%, but will typically measure this from 10 to 90% of the amplitude. And this is illustrated in the picture on the top right hand side. We start measuring when we hit 10% of the amplitude and stop measuring when we hit 90% of the amplitude. And this is true for both rising and falling edges. Once we've gathered that from our square wave or rather our trapezoidal wave, there's a very neat rule of thumb that estimates what our maximum frequency content is due to these rising and falling edges. And again this rule of thumb is essentially derived by a FIA analysis showing what's the maximum frequency or what is a knee frequency. Essentially the rule of thumb and there are various variations of this but this is a more strict one. The maximum frequency this time given in gigahertz is 0. 5 divided by the rise or fall time and again whichever is shorter because the shorter rise or fall time will indicate a higher maximum frequency and that rise or fall time is in nanconds. So f max in gigahertz is about 0. 5 divided by the rise or the full time in nanconds. Another really useful rule of thumb is because as we'll see finding rise or fall times from data sheets and for certain parts can be a bit difficult. If you don't have that information you might have to go by the clock period to figure out what the edge rates need to be. If we think about it, if we have a very short clock period, for example, indicated by capital T, then our edge rates have to be faster and faster to get to the high and low levels as quickly as they can for that specific clock period. Of course, this isn't fixed, and this is kind of approximately a best case. So, be careful when using this. But approximately, if we have the frequency of the clock, then our rise and fall time has to be approximately 1 / 10 * the maximum clock frequency. The frequency again is in GHz and the rise in full time is in nanconds. In the top right hand side, we have a plot of the time domain of a typical let's say a clock signal. Amplitude on the y-axis, time on the x-axis. We have the rise time which in this case is equal to the full time indicated with tr and we have the period indicated by capital t. If we do a fer analysis, so converting this into the frequency domain, we can see an approximate result on the bottom right hand side. We have amplitude on the y-axis and on the x-axis this time we have frequency. We can see the maximum frequency defined by the clock period is actually just 1 / t indicated by fn and this is pretty much the start on the left hand side of the graph. The rise time gives us the knee frequency which we will be using as the maximum frequency rule of thumb and this is shown far to the right of our clock frequency and this is why the edge rates are much more determining in overall maximum frequency content of a digital signal. Here are some examples. If we have a 1 ncond rise time using the rule of thumb again 0. 5 / 1 in gigahertz gives us a maximum frequency of 500 MHz and that's quite significant 1 ncond these days is not too fast many microcontrollers have one or nancond rise and fall time GPIOs many modern FPGAs and system on chips however have rise and fall times in the hundreds or tens of picosconds using the same formula of fmax is. 5 / t rise or all to 100 piccond rise time. So 0. 1 nconds, we get an fmax of 5 GHz and that is quite significant. Again, this doesn't matter if the clock is 1 MHz or 100 MHz or 1 GHz. The rise times and fall times are important. Similarly, we can also use the clock to rise time rule of thumb. So

for example, if we have a 100 MHz clock, plugging this in, so 100 MHz is 0. 1 GHz using the clock to rise time rule of thumb. So it's 1 / 10 * 0. 1 which is 1 ncond. Again 1 ncond in the rule of thumb or the maximum frequency content gives us 500 MHz. So this is for example how 100 MHz clock is not the maximum frequency but rather determined by an approximation of the rise and fall times which give us a much higher frequency. And this is very important when it comes to controlling impedance, minimizing reflections and so on. Once we have our maximum frequency content, for example, for a digital signal, the actual calculation for critical length is then pretty much the same as the analog equivalent. In this case, we use F max, which we derive from the rise and fall times. Basing this on a true example, for example, a typical modern microcontroller with a very simple in quotes GPIO, which we just use maybe to toggle an LED on or off, might have a rise time of 1 ncond or faster. Again, using the rule of thumb means that our actual maximum frequency content, even if we're just toggling an LED, might be 500 MHz. Calculating the critical length of that, so speed of light divided by 500 MHz, assuming an outer layer, we get a critical length of only 28 mm on an outer layer and on an inner layer, a critical length of 23 mm. This is quite significant. If we root over 3 cm in length on an outer layer or over about 2 1/2 cm in length on an inner layer, even for this GPIO, we have to deal with reflections, possible signal integrity, and EMI issues. Therefore, we might even have to impedance control these tracks. Again, another reason to keep all signal traces as short as you can. However, many modern microcontrollers as well also have options for setting the slooh rate or the rising and falling edge times via a software setting, essentially decreasing or increasing the drive strength. So many times it can pay off to either choose microcontrollers that have slower edge rates or a software controllable edge rate to counteract this problem. This is an image I took from a Cardly seminar I attended and this shows various types of logic and digital logic compared to the rise time on average they might have at the IO's and then what that means for the critical lengths for inner and outer transmission lines or traces. What's interesting of course as we saw before also that the critical length of an inner layer trace is less typically than an outer layer trace and this is due to the higher dilectric constant on average. Starting at the top, we could have maybe simple microcontrollers, memory, and so forth. And these are in the couple nanconds rice time leading to fairly generous critical lengths such as 10 cm, 20 cm down to about 7 or 8 cm. What we saw previously and also true for modern MCUs, FPGAs, and microprocessors, we start getting to nanconds and subnosecond regions. And this again is where the critical lengths start becoming rather short indeed. example only a couple of centimeters. Even worse, however, when we're dealing with very high-speed FPGAAS, system on chips, anything that processes in the gigabit range, we need very, very fast and short rise and fall times to keep up with these clock rates. For these devices, signal integrity and EMI issues need to be counteracted all the time. You can see even for 10p, which is incredibly short rise time, we have 0. 33 mm or 0. 4 4 mm of critical length, but this is a nice illustration of how rise time really makes a difference on the critical length. I hinted at before that rise and fall times for IC's and their specific pins or IO's are usually fairly hard to find. Typically, if we're looking at a data sheet, the maximum rise and fall times are if they even given a best case, and that is pretty much useless. If they're giving a best case of for example 5 nconds as the maximum rise time well if they don't give us a minimum rise time that could be maybe 10 ps and then we're a bit screwed. An example of where we might find this information let's look at for example this USB 332 which is a USB highspeed physical layer which I've also used in the set design. Opening the data sheet, looking at various tables, for example, at dynamic characteristics, we can see some hints at rise and fall times. USB has various different speed grades. For example, high speed, low speed, full speed. And depending on the setting, we get different rise and fall times. For example, for the full speed setting, which is actually pretty slow, we get away with a much slower rise and fall time. So, our minimum is 4 nconds and our maximum is 20 nconds. Of course, then for our critical length and maximum frequency content calculations, we need to use the worst case, which is the minimum rise time. The shortest rise time gives the maximum frequency. So, we'd use 4 nconds. If we go to low speed, which is even slower than full speed, of course, we can get away with a much slower rise and fall time. Here, going to a minimum of 75 nconds. And again, this is an illustration how signal speed does relate to edge rates.

and that for faster clocks we need faster edge rates and for slower clocks we can get away with lower edge rates. However, looking for example at the high-speed output driver we can see that the rise time for the USB differential pair is 500 picosconds. That means actually for USB highspeed layer which only goes up to about 480 megabits per second. This rise time of 500 picconds means our maximum frequency content is up to 1 GHz using our rule of thumb. That's pretty impressive and not really in a good way. However, if you find a data sheet where you can't find these rise and fall times and maybe only a best case, which isn't really useful, we can look at IBIS files and these are simulation files essentially provided by the IC manufacturer that characterize specific IO's under the specific device terms of capacitances, inductances and so on. These can then be used to extract rise and fall times. One caution however the IV specification typically is between 20 to 80% rise and fall times whereas our formula use 10 to 90% rise fall times. So we need to do a linear mapping from 10 from 20 to 80% to 10 to 90% full times. I won't go into further detail in this course. I've made a video on this and how to calculate Ryzen full times using IBIS files. I'll leave the video link in the links and download section below this lesson. But if you'd like to search for it, it's Phil's lab video number 64 called PCB design for EMI and SI. And this goes through a practical application and calculation. How to find an IBIS file and then how to get a rise and fall times for any part from this. Now that we've seen why impedance control if traces is necessary in essence to avoid reflections, minimize our impedance mismatches and discontinuities which otherwise would lead to signal integrity and EMI issues. And we've also seen when this is necessary. And this we arrived at by looking at the critical length, seeing the difference between analog and digital domains. The question now is how do we match the impedance of our traces for example to the driver impedance to the source and then also to the load impedance. This overall process is then called controlled impedance traces. The way we then control the impedance of a trace is via various parameters. First of all, the trace geometry. So how wide a trace might be. We can control them by the buildup. So, how close to a reference plane might a trace be? As well as the stackup is a trace surrounded by one reference plane, two reference planes and so on. There are many different types of controlled impedance traces which often times known as transmission lines. The ones we'll be looking at and the ones used most commonly especially in highspeed digital designs are named micro strip which is an outer layer trace. As we can see on the right hand side we have a trace surrounded essentially by air by the surrounding medium then a dilectric material for example a pre and then a reference plane below. On the other hand we can have stripline traces which essentially mean an inner layer trace. We have a trace in the middle. We have a dialectric material above and below as well as reference planes above and below. These dialectrics can also be asymmetric so they don't have to be the same thickness and often times they aren't. For our cases, the transmission line will be defined by a forward path, our trace and a return path, which can either be a plane or a set of planes. And these exist both for the single-ended versions and also for differential versions. We can do impedance control for both. And I'll show you that in more detail very simply without providing any derivations. A trace impedance where the characteristic impedance is typically determined by Z KN is approximately equal to at high frequencies so at AC by the inductance and the capacitance. Specifically, the impedance is the square root of the inductance per unit length divided by the capacitance per unit length of the trace. Because these are both per unit length measures, the lengths cancel out and therefore the impedance of a trace is not really dependent on the length of it. Therefore, if we can size the trace appropriately, so we can adjust the inductance of the trace as well as the capacitance of the trace, we can then through that define what impedance, for example, the driver sees and what impedance a load might see. A quick tip as usual because you want to gain some intuition of how to size traces and how that influences the impedance properties. Inductance L essentially has to do with loop areas. So, for example, distance to reference planes. If we increase the distance, we increase the loop area and we increase the inductance. On the other hand, capacitance can be controlled by the surface area. So for example, if we widen the trace above a reference plane, the trace might have more capacitance with respect to the reference plane and therefore we lower the impedance. But more on that later. Let's start with micro strip traces. Again, this is an outer layer trace as shown on the right hand side. We have a trace on the top which is surrounded by some sort of medium typically air which has its own dialectric constant epsilon0 and a dilectric material the PCB material below which again has a different dilectric constant. The effective dilectric constant in which this trace is effectively embedded in is a ratio

and a mix of the air dilectric as well as the dialectric of the PCB material and this can be quite difficult to calculate but there are calculators on the internet or in your ECAT tool. What's very important again is the reference plane which is the return path which is directly adjacent to the trace. The trace and plane are separated by a dialectric. Then if you want to calculate our impedance our Z KN the square root of the ratio of inductance to capacitance. This is dependent on the trace width the height of the trace above the plane as well as the dialectric constants. Again thinking of inductance as loop area capacitance to do with surface areas. Increasing the width typically increases the capacitance and thus reduces the impedance. And increasing h the distance between the trace and plane or the thickness of the dialectric increases the inductance and therefore increases the impedance. Let me show you how to calculate a trace width. Now for this we'll just be using the stackup with the set bread as an example. Let's look at the top layer trace. On the top layer one we have a signal layer. Below that we have a pre of a certain type and below that we have a reference plane which in our case is ground. What is important for us is the thickness of the dilectric. As we can see here it's 70 microme or 0. 07 mm. The dilectric constant of that material is also important which is four. What we then first need to do is calculate the effective dialectric constant. Remember it's surrounded partially by air and partially the fields are embedded within the dialectric material of the PCB. We can use an online calculator such as this one. If you just search for effective dilectric constant calculator, we'll type in the dilectric constant of our prep prag which is four. And we can type in the height or the distance from the trace to the plane which is 0. 07 mm. Now we have a slight problem. This calculator is also asking us for the width of the trace. However, trace is something you want to calculate for our controlled impedance. Unfortunately, the width of the trace also plays in to what the effective dilectric constant is. So for example, if we leave the trace width at 0. 3 and click calculate, we can see the effective dialectric constant is about 3. 27. If we increase the trace width, it's about 3. 4. And if we decrease three. However, we can just use any old micro strip impedance calculator. And these will have the equations built in to also calculate the effective dialectric constant. And that we just have to type in our various geometry parameters. In this particular case, they also want the trace thickness. And for us, that was for example 1 oz weight copper, which gives us a thickness of 35 microns as we saw before. That's what we entered here. We entered the substrate height, which is 70 microns. And then we can play around with the trace width, as well as entering the substrate, which is our pre prag dilectric constant, which was four. For 0. 5 mm trace, given these various trace thicknesses, substrate heights, and dialectric constants, we get an impedance of about 20 ohms. We'll see later on how we can actually get the required impedance values for specific buses. And this depends, for example, if we're rooting PCI Express, HDMI, USB, and so on. But typically for single end impedance, single-ended meaning we only have essentially one trace, we typically want to have a target impedance of about 50 ohms. To get 50 ohms, we'll have to reduce our trace width because that'll increase the impedance. So, if we go from 0. 5 mm to 0. 3, we've already gone to 29 ohms. If we go to 0. 12 mm, we're pretty much spot on 50 ohms. I'd strongly suggest playing around with one of these micro strip impedance calculators to see what effect the various parameters have on the overall impedance. But this is how we can use for example the dialectric thicknesses, different dilectric materials and finally the trace width to alter the impedance properties of the trace to find out what the actual trace impedance needs to be if this is for single-ended or differential. We need to find some user guides or some references. This could be the relevant standard for example PSCI stress or USB or quite nicely again zylings provides various user guides. So, for example, user guide 933 for the Zinc 7000 series PCB design guide, which we saw previously. Then we can scroll through various sections. For example, if we're concerned about routting our DDR memory, which we'll see later as well, we could go to the dynamic memory section. Scrolling further down, for example, to page 65, we can see a section on DDR trace impedance. For various different types of memory, for example, DDR2 low power DDR2 or DDR3 low voltage, we need different single-ended or differential impedances. In addition to the absolute value, we always have a tolerance with our impedance as well. The tolerance has to do essentially with what magnitude of reflections and discontinuities are accepted for signal integrity and that this device then will still function. Tolerances also play into when we come to manufacturing because [clears throat] manufacturing for example a 0. 1 mm trace is very hard and we might have tolerances within that. So if we have a 0. 1 mm trace that gives us maybe 40 or 50 ohms that trace

could vary within 10% and that will of course change the variation in the control impedance or our characteristic impedance. But in this way, I would then look up all of the devices I'm rooting, all of the high-speed devices, if I have DDR, what type of DDR, and this lets me find what value of impedance I need for that specific signal. Then I would use one of these micro strip or strip line later, we'll see impedance calculators to find the required trace width. Now, this is all just a start indication. I would do these preliminary calculations to see approximately what my dialectric materials have to be, how thick they have to be, and how wide my traces need to be. The actual calculations we use at the end will come from the manufacturer as I'll show you in my ECAD tool. And this depends on the tool you're using of course. But in Alum Designer, for example, I have a separate impedance tab where I can type in my trace width and the tool itself will then calculate the impedances approximately with a 2D field solver. Again, this needs to be verified with your manufacturer. Therefore, for me, my trace width is about 0. 1 mm and gives me an impedance about 50 ohms. And this is what I verified with a manufacturer. You might be thinking. 1 mm is very thin and very narrow as a trace. But remember this is application specific. The reason I have these very narrow controlled impedance traces is because of the routting constraints of my design. Simply to fan out this BGA and to have these traces impedance controlled means they need to be very narrow. As an example, for example, these DDR3 traces or for example these QSBI traces on the right hand side, we can see the width is pretty much. 1 millimeters all of the time. Again, because these are controlled impedance traces, all I have to do is talk to my manufacturer, do some preliminary checks with calculators selecting my buildup. And then to route a controlled impedance trace a micros trace on the layer below I need a solid reference plane and above I root width I calculated from my calculator or given from my manufacturer. As you can see all of these controlled impedance traces have the same width and are rooted over a solid continuous reference plane further away from voids if I can. And that's how simple it is to control impedance of traces. We need to figure out our buildup, the heights of the dialectric width for trace using an impedance calculator and then also confirm that with our manufacturer who might adjust our trace widths, but more on that later. Then we have a solid reference plane and we route over that reference plane with a trace width we calculated. And there you go, you have a controlled impedance trace, in this case a micro strip trace. Micro strips might have some disadvantages though. As we saw, these are directly exposed to the environment. So that will have more field spread because we only have one reference plane above or below the trace. Another tip is because any conductors close to the trace will throw off the impedance profile. So if I bring a trace very close to this or if I pour copper around this, for example, a ground copper paw, this will change the impedance profile of this trace. Therefore, in the picture on the bottom right, you can see I've pulled away from this controlled impedance trace, the copper paw around it. And I'd recommend a minimum 3H pullback. So keep the copper surrounding this trace a minimum of three times that dialectric thickness away from that trace either side. For example, this eMMC clock trace I've rooted out again the controlled impedance trace with a specific width rooted above a ground reference plane. And any copper pole I have close I've kept sufficiently far away at least 3H spacing away from my controlled impedance trace so it doesn't throw off the impedance profile. The second type of controlled impedance trace we'll look at are what's known as stripline traces. These in comparison to micros traces which are out layer traces, stripline traces are simply inner layer traces which means we have a dilectric PCB material above as well as below and then we have reference planes both above and below. Often times our dialectrics will have different material properties. So different dialectric constants as well as different heights. So often times you'll see this referred to as an asymmetric strip line. The calculations again for this are quite involved especially since we have a few different materials and different thicknesses and so on. But essentially the principles are very similar to the micro strip. We have reference planes two in this case which perform our return paths and we have a trace essentially embedded right in the center of a specific width and also a thickness which is of lesser priority. The width and the dilectric [snorts] constants as well as the heights are the main determining factors which determine the impedance characteristics of that specific trace. Again, we can use an impedance calculator to do all the hard work for us. Simply doing a web search, we can find symmetric and asymmetric strip line impedance calculators. I'll just show you the symmetric version for now as this has fewer parameters of course and just act as a demonstration. Once I have my impedance characteristics and the ones I require for micro strip or strip line, what matters for example are the required impedance specs and the tolerances and these are given again depending on the signal and system you're rooting. Once I have that information, I would then try and figure

out approximate trace widths depending on substrate heights, dilectric heights and so on to find if I can make this work with my particular buildup. As you might have seen, I'm using very thin dialectric materials, sometimes even below. 1 mm. And this is because I have very narrow trace widths in general for the reasons we saw earlier. Very thin dialectrics mean we can typically make our traces narrow as well for a given impedance spec. As an example for an in layer trace we might have a trace thickness of 17. 5 microns which is/2 copper. Our substrate height either side remember this is strip line. We have dilectric above dilectric below might be something like. 13 mm. The substrate dilectric we'll just keep at four as well. And then we can play around with different trace widths. For example, 0. 5 mm will give a very low impedance of 8 ohms. Therefore, reducing that trace width as was the case with the micro strip should increase our impedance. So, going down to 0. 3 mm, we get 22 ohms. Going down to 0. 1 mm, we get pretty much 50 ohms. Now, you can see I didn't choose these substrate heights, substrate dialectrics, and trace width arbitrarily. There's a reason why 0. 1 mm in combination with these parameters give 50 ohms. because that's pretty much what we're using in the set bread as well. So any layer, for example, layer 8 that has a reference above and a reference below or even layer 4 which has a power reference above or power layer below. You can use these impedance calculators for strip line. Again, the tool I'm using, Alum Designer, has this built in. So I can type in a trace width and it'll give me the impedance of that trace. But again, calculators are only used to get you approximately there. You should trust and ask the manufacturer for their impedance calculations given the buildup for example they might suggest and that you've adjusted with to then route a stripline trace. It's as easy as a micro sip trace except that it's embedded within the PCB. So if I go to layer 8 we know that layer 7 is a solid ground plane solid reference plane. Layer 9 is a solid reference plane solid ground plane. So layer 8 all of these that are beneath that sandwich so to speak are stripline controlled impedance traces. Therefore, all these traces you see here, for example, of the Ethernet fi routting are 0. 1 mm to match that 50 ohm spec. Same goes for my QSBI connections. They are stripline traces matching the 0. 1 mm and thus 50 ohm spec. Strip line traces, as we touched on before, are buried and shielded, meaning that we typically have an improved EMI performance because we have closely coupled planes directly above and below, which reduces field spread. The problem with stripline traces however is that we need to get inside the PCB and that means v have their own problems. They might leave stubs might have parasitic inductances capacitances and so on. So there's always this trade-off. The same thing that applied to microscrip traces applies to strip line as well. Avoid copper close to the trace because this throws off the impedance. Again we want a minimum about three height of the dialectric pullback. And this element you can see exactly here. So for example, I have various controlled impedance traces uh rooted as strip line. And anytime I have a copper paw around it, I'm pulling this away from these controlled impedance traces as not to throw off their impedance profiles. To do that, typically I'll do something known as a polygon paw cutout and I'll just draw that around those traces to make sure I can do an arbitrary copper fill or pour. And that will then not pour close to my controlled impedance traces. We've now just looked at micro strip and strip line controlled impedance traces with respect to single-ended signaling. So we have individual traces with their reference planes. However, in PCB design oftent times also with high speeds and more robust signaling we are concerned with differential pairs. And of course those we can impedance control as well. In comparison to for example single-ended micro strip or single-ended strip line we have an additional parameter and that's known as the trace spacing. This is illustrated in the bottom right hand side picture where we have two individual traces. So trace one and trace two with a reference plane below separated by dialectric material with thickness h. These constitute the negative and positive portions so to speak of the differential pair. The distance between the trace one and trace 2 little d influences the differential impedance. It's important to note, however, that on a PCB, this differential pair, although we call it that, are effectively still two individual single-ended signals, which predominantly don't reference each other. Trace one, for example, on the left hand side references the plane below, and trace two on the right hand side references the plane below. The energy, the fields, and the coupling are predominantly between the individual traces and the plane below, and minimally between each trace. So about 80 to 90% of the energy in coupling is from an individual trace to the plane below. This is very different for example to a twisted wire pair where the coupling is directly between each other. But for PCB we can see these as two individual single-ended signals which are separated by distance D. The differential impedance then is predominantly defined by this single-ended impedance. The impedance we

saw for example Z in micro strip and strip line single-ended controlled impedance. However, we subtract from that a coupled impedance. The coupled impedance depends on the trace spacing between the traces here. And this is little d. The closer we bring these traces together, the tighter the coupling is and the higher for example zed coupling is. The further away these traces are from each other, the larger little d is, the less coupling we have between the individual traces. Therefore, our differential pairs are defined predominantly by z, our single-ended impedance. But we have this second parameter which we know as the differential impedance Z diff. Very simply Z diff is 2 times the difference between single-ended minus the coupling impedance. And again Z N pretty much dominates. This brings in some more complications because now we have to choose an additional parameter. We need to know what our single-ended impedance needs to be as well as our differential impedance and from that we choose trace widths. the width between them will always be the same and then we always have to choose the distance between these two traces of width W. My way of doing this and I'll show you an example is to choose the trace width first again like we did with single-ended signals. This is again dependent on some sort of single-ended impedance requirement which we can read off from a spec sheet. Once we have our single-ended trace width and then our single-ended impedance, we can adjust the trace spacing little D to match our differential impedance requirement. And again, this is based on the required spec. So PCI Express, USB 2. 0, HDMI, and so on. Again, looking at a fairly random document, we'll look at this PCI Gen 4 application note, and we can go to the PCI Express standard in section 2. 1. In this, we can see, for example, the trace impedance requirements for PCI Express Gen 1 and 2 as well as PCI Express Gen 3 and 4. And from this, we can straight off read the impedance requirements. Say for gen 3 and four we need 85 ohms differential with a maximum allowed tolerance of plus - 5%. So approximately we can go between 80 and 90 ohms differential. But then of course we also have the single-ended impedance requirement which is dependent on the trace width and the distance to the reference plane below. This is speced at 42. 5 ohms again plus - 5%. That's why we have these two difference app requirements. One again is to do predominantly with the trace width and the other is to do with the trace spacing. So we want to select our trace width first and then our trace spacing. And keep in mind this equation that the differential impedance is 2 * the individual single-ended impedance minus the coupling impedance. So we choose N first and then we adjust the distance between the traces to change our coupling impedance. Also remember that we calculated for example for our single-ended 50 ohm lines a single-ended impedance for example for an outer micro strip layer single-ended impedance 50 ohms gives about. 1 mm trace width I'll show you a differential trace width impedance calculation specifically for USB 2. 0 highspeed for example as this is a very common interface simply searching for example USB 2. 0 O highspeed impedance spec ths up various different documents. From this we can see a trace impedance specification and you'll find this pretty much for every interface. We can see we need 90 ohms plus - 15% differential and 45 single-ended. In comparison to the PCI Express specification we saw earlier, we can see that these are far looser constraints because this is a far lower speed interface. So what we need to do is 90 ohms differential and 45 ohms single-ended. What we're actually going to do is do a 50 ohm single-ended with a plus - 10% tolerance. Because we have 50 ohms already in our design as these traces, I don't want to design a 45 ohm impedance control trace because as we'll see later when we discuss this with the manufacturer, we need to list what impedances we need. It's much easier for us because this USB 2. 0 is actually not that fast to simply do a 50 ohm single-ended signal and then match at 90 ohms differential. Again, we'll use an impedance calculator to do so. For micro strip differential trace, this might be called something such as an edge coupled surface micro strip. We enter the usual parameters such as copper thickness, isolation height, meaning the distance between our traces and our reference plane, which in our case for the set bread for top layer or bottom layer is 0. 07 mm. The dialectric constant is four. Keep in mind the calculations used in various of these calculators will differ depending on who offers them and who's implemented them. These are just meant as a rough estimation of track width and track spacing. Again, talk to your manufacturer to find out the proper values so to speak. We'll start off with a track width which gave us 50 ohms nominally as our single-ended impedance. So, we're varying W. And this is what I would start with. So, start with your single-ended impedance matching the requirements. The calculator is showing us a bit higher. So about 56 ohms, but remember this will depend on which calculator you're using. So as long as we're, you know, plus - 10%, we're probably in the right ballpark. It isn't

about being precise. It's about getting into the right ballpark and then asking the manufacturer. Then we can play with a track spacing. In this case, they've called this parameter S. For 0. 1 mm track spacing, our differential impedance is then 112 ohms approximately. Remember this is 2 * Z N minus the coupling impedance. As you can see the differential impedance as we saw before is approximately 2 * Z N minus Z coupling. So Z diff is always dominated by Z N. If we move the traces further away we can see we have less coupling and we have a higher differential impedance. If we bring the traces closer again of course we'll have more coupling between the individual traces themselves and therefore we will lower the differential impedance. And this is how we then can play around with the track spacing to match our differential impedance requirements. I've done the exact same thing in my E-cat tool where I have my width, my traces for an external layer. This is 0. 1 mm again to match the 50 ohm spec. And then I played around with my trace gap to get me around 90 ohms. And this is what I confirmed with my manufacturer as well. And this is my process regardless if this is PCI Express, HDMI, USB, and so on. We also spoke previously very briefly about power planes as references. I'd like to just add some more details now. Power planes can be used as references, but typically they are worse references or return paths than a ground or 0 volt plane. Importantly, when we're switching layers and references, as we've seen also with transfer VAS, going from a ground reference to ground reference is okay. With a signal via, we simply place a transfer a grounded via close to that signal via. However, we get problems when we're changing, for example, from a ground reference to a power reference or power to a ground or power to power. What do we do then? We can't place a via with just a single potential. What we then have to do is place a stitching capacitor which has limited high frequency performance which can then lead to EMI or signal integrity issues. Additionally, on the top right hand side and what we've seen before is the power plane for the set red PCB and of course you might have multiple power planes in your design. This is heavily segmented. We have various different nets of 3. 3, 1. 8, 1. 0 volts and so on. So if our forward path, our traces are rooted adjacent to this layer and use this power layer as a reference, we will be crossing various splits. For micro strip, this is a big nogo and we definitely shouldn't do this. For micro strip, we are a bit more relaxed. Of course, depending on the repeated specs and the system we're rooting, but since we're rooting over splits, we'll have an impedance continuity. For example, at the top reference, we might have this plane and on the bottom reference, we might have a solid ground plane for a stripline trace of a certain layer. As we also saw in the set, this is again why in the sett layer 4 which is surrounded by this heavily segmented power plane as well as layer 5, this ground plane only contains fairly non-critical signals. So keep this in mind if you're trying to use or want to use power planes as references. They're not ideal for any high-speed signals and sensitive signals that I want to route for example a strip line. I definitely suggest having two ground planes adjacent. Here are also some practical considerations that we have to consider when we're dealing with controlled impedance. For high density and fine pitch designs, controlled impedance traces will be very narrow to be able to fit as we saw with the BGA fan out for very fine BGAS or QFNs and so on. meaning that the trace width will be for example 0. 1 mm maybe a bit wider. Narrow traces as we also saw typically mean thin dialectrics. We saw for example the dilectrics we're using some of the pres were 70 microns thick. This will and can be a cost adder and also might limit the material selection we're available. As you saw I had to use 1080 prep prag to be able to get these thin traces and 1080 we saw the weave wasn't that great. Additionally, manufacturing tolerances impact narrow traces which then therefore impact the impedance of that trace itself and the impedance tolerance. This is also a reason why RF boards are often two layers which have a very thick dialectric. That means we need very wide traces to get a certain impedance. Example 50 ohms. Example 0. 6 mm versus 0. 1 mm 50 ohm impedance control trace. If we chop off 0. 05 mm of the 0. 6 6 mm trace comparatively to the 0. 1 mm trace, it's going to affect the 0. 1 mm trace a lot more. Another consideration might be that of skin effect. Skin effect, very simply speaking, is that the higher the signal frequency, so going from let's say 1 kHz up to several GHz, the smaller the cross-section of the trace is actually utilized, all of the current carrying capabilities of the trace are limited to the external perimeter or external small cross-section of the trace. This introduces losses and is even worse for narrow traces such as our 0. 1 mm traces. Finally, and I've alluded to this many, many times, is the importance of speaking to your manufacturer before and

during the design, especially when it comes to buildup and your impedance control requirements. You can ask them what materials are available and they can suggest suitable ones for your needs, what buildups are possible. You need to tell them which layers require impedance control and which layers are used as references. where you can tell them what target trace widths you need. For example, I need 0. 1 mm traces at 50 ohms because of my fanout constraints. And they will provide you also with impedance control calculations. I'll show you all of this in a practical example in just a second. How I communicated this with PCB way for example. Another tip is to reuse buildups and stackups from previous designs if possible. For example, this set bread is a 10 layer board with certain impedance control requirements. And it's very likely that I'll need to use a 10 layer board in the future with very similar impedance control requirements. And this could be a great starting point to see what's possible and what has already been manufacturable. This is also good for reusing impedance calculations as well as cost estimates. However, this doesn't mean that your stackup won't change and that your manufacturer might not be able to produce that maybe in a year or two time. Always confirm with your manufacturer that this is still possible.