Validating PCIe Performance

Cadence provides IP solutions  across all major standard with   unsurpassed reliability to help accelerate  our customers time to market. I'm John Tam,   product marketing group director and I'm  here with Leith in our Bangalore labs.    He's a design engineering group director  in charge of product validation. Lather,   tell us what you're going to show us today.   Thanks, John. At Cadence, we not only build IP,   but we build test vehicle that enable us to  comprehensively verify our solutions against   the latest commercially available solutions in  the market. Let's look at the demonstration that   we have set up today. Here we have an ASUS  motherboard that is PCI 5. 0 compliant and it   is connected to a Broadcom Atlas 3 suite which is  PCI 6. 0 compliant. On the other end of the switch,   we have five different cadence PCI endpoints. So  as you can see we have a representation of a real   world system where we have a motherboard talking  to several different endpoints through a switch. Let us now initialize the entire system. As  you can see all the endpoints have successfully   linked up. So we have a Niger N5 with a gen 6x8  link. An aura N5 in E3S form factor with a gen   6x4 link. Then we have a Piper N3 with a gen 6x1  link. We have an agara 3 nanometer with a gen 6x8   link and finally a whistler in 3 nanometer with  a gen 5x8 link. A lot of it that is great. What   do customers care about electrical performance?   There are several important electrical parameters   that the customer care about. The primary among  them being the receiver margin. Let's look at the   receiver margin on one of the PCI 6. 0 links here.   The cadence PCI 6. 05 I has a has several built-in   functions to evaluate the receiver margin. On  the left, we see a non-destructive eye plot which   clearly shows a good linear eye. On the right,  we see the histogram of the data at the output   of the DSP which clearly shows four different  PAM for levels with good margin between them.    This is one of the tools that we use to evaluate  the margin on the receiver which is the critical   parameter in ensuring the link's robustness.   So lava real deployments need to be robust with   changing links and changing states you know all  the time. So how do we test for that? Because we   build our test vehicles with the entire protocol  stack. It gives us the ability to emulate several   of these real life situations where we can perform  rigorous systems stress testing with commercially   available latest platforms. Let's look at some  of the such use cases. Now I will run a link   enable disabled test on one of the gen 6. 0 by  eight links. In our regular product validation,   we run these cycles for millions of times to make  sure our product is healthy and robust. So as you   can see here, the system is going through several  cycles of link enabled disabled system and you can   see the different transitions of the PCI FM LTSSM  here. Having the ability to perform such tests and   with a with the cadence test vehicles is a clear  differentiator and this is what really enables us   to be market leaders in the PCIe segment. As you  see here, we've just successfully completed 100   iterations of the link enabled disabled test. Uh  let's now look at another use case which is the   hot reset test. As you see, the hot reset test has  also passed successfully. Another common use mode   is the low power entry and exit. Cadence offers a  very competitive solution when it comes to lower   power. Thanks La for showing us a real-time demo.   Really shows and it will demonstrate Cadence IP   solution for AI. For more information, you  can find that on www. padence. Hadens. com