RISC-V 2026 Update

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RISC-V 2026 Update

ExplainingComputers 19.04.2026 60 833 просмотров 5 035 лайков

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RISC-V annual review, including RVA23 silicon, AI, RISC-V in automotive, and an interview with RISC-V International CEO Andrea Gallo. If you like this video, you may also be interested in the following ExplainingComputers episodes: "Why RISC-V Matters": https://www.youtube.com/watch?v=4TmHSsIU1ns "RISC-V 2025 Update": https://www.youtube.com/watch?v=9s8hPmCZ0mk "RISC-V 2024 Update": https://www.youtube.com/watch?v=f6mPK3QCrBo "DC-ROMA RISC-V Laptop II": https://www.youtube.com/watch?v=3mhd98AGNXQ "Milk-V Jupiter RISC-V PC Build": https://www.youtube.com/watch?v=LX9Pz1TmEww And you can find all of the ExplainingComputers RISC-V videos on this page: https://explainingcomputers.com/riscv_videos.html KEY REFERENCES RISC-V International Annual Report: https://riscv.org/about/annual-report/ “Building a RISC-V Core” and other free training courses: https://riscv.org/community/training/ FULL REFERENCES BY VIDEO SEGMENT INTRO: Scaleaway RISC-V cloud services: https://labs.scaleway.com/en/em-rv1/ RISC-V PROGRESS: SHD Group predictions: https://static.sched.com/hosted_files/riscvsummit2025/44/Richard.pdf Meta acquires Rivos: https://www.lw.com/en/news/latham-watkins-advises-meta-in-acquisition-of-rivos Qualcomm acquires Ventana: https://www.qualcomm.com/news/releases/2025/12/qualcomm-acquires-ventana-micro-systems--deepening-risc-v-cpu-ex Arm stock falls following Qualcomm Ventana purchase: https://www.techradar.com/pro/arm-sheds-billions-in-market-capitalization-after-qualcomm-hints-at-risc-v-adoption-with-ventara-micro-acquisition First RISC-V International annual report: https://riscv.org/about/annual-report/ RISC-V on path for ISO: https://riscv.org/blog/risc-v-jtc1-pas-submitter/ RISC-V & AI: Meta MTIA v1: https://ai.meta.com/blog/meta-training-inference-accelerator-AI-MTIA/ Meta MTAI March 2026: https://ai.meta.com/blog/meta-mtia-scale-ai-chips-for-billions/ SiFive Intelligence Family Second Generation: https://www.sifive.com/press/new-x100-series-second-gen-intelligence-family Semidynamics: https://semidynamics.com/ai-systems Esperanto Generative AI Appliance: https://www.esperanto.ai/products/ Google Coral NPU: https://developers.google.com/coral/guides/architecture RVA23 SILICON: RVA23 Ratified: https://riscv.org/blog/risc-v-announces-ratification-of-the-rva23-profile-standard/ Spacemit K3: https://www.spacemit.com/products/keystone/k3 Akeana RVA23 tapeout: https://www.akeana.com/akeana-tapes-out-highest-performance-rva23-alpine-test-chip/ Tenstorrent Ascalon availability: https://tenstorrent.com/vision/tenstorrent-announces-availability-of-tt-ascalon Spacemit: https://www.spacemit.com/ K3 datasheet: https://cdn-resource.spacemit.com/file/chip/K3/K3_brief_en.pdf Milk-V Jupiter-II: https://milkv.io/jupiter2 DC Roma RISC-V Laptop Mainboard III: https://deepcomputing.io/dc-roma-risc-v-mainboard-iii-unveiled-at-fosdem-powered-by-spacemit-k3-for-framework-laptop-13/ Tenstorrent Ascalon X datasheet: https://cdn.sanity.io/files/jpb4ed5r/production/ffe5aee223d2bd8c4d44611a902ff62a5474e122.pdf T-Head C950: https://www.xrvm.cn/product/xuantie/C950 C950 Datasheet: https://regmedia.co.uk/2026/03/25/supplied_xuantie_c950_spec_sheet.pdf RISC-V & LINUX: RISE Project: https://riseproject.dev/ Ubuntu RISC-V: https://ubuntu.com/blog/tag/risc-v Red Hat RISC-V: https://developers.redhat.com/products/rhel-riscv Debian RISC-V: https://wiki.debian.org/RISC-V Fedora RISC-V: https://fedoraproject.org/wiki/Architectures/RISC-V OpenSUSE RISC-V: https://en.opensuse.org/openSUSE:RISC-V Arch Linux RISC-V: https://archriscv.felixc.at/ Bianbu OS: https://www.spacemit.com/community/document/info?lang=zh&nodepath=software/SDK/bianbu/root_overview.md RISC-V, RISE & Yocto: https://riscv.org/blog/risc-v-international-and-the-rise-project-join-forces-for-yocto-project-support Yocto Project: https://www.yoctoproject.org/ More videos on computing and related topics can be found at: http://www.youtube.com/@ExplainingComputers And more videos on film and other making, plus retro tech, can be found on my Christopher Barnatt channel: http://www.youtube.com/@ChristopherBarnatt Chapters: 00:00 Titles & Intro 01:46 RISC-V Progress 04:24 RISC-V in Automotive 07:23 RISC-V & AI 10:29 RVA23 Silicon 16:06 RISC-V & Linux 18:02 Exciting Times #risc-v #riscv #rva23 #ai #automotive #cloud #k3 #spacemit #ExplainingComputers

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Titles & Intro

Welcome to another video from explainingcomputers. com. This time, it's our 2026 RISC-V annual review. RISC-V is an open standard instruction set architecture or ISA that provides an alternative to the closed ISAs used in today's x86 and ARM processors. Today, most desktops, laptops, and servers have an x86 CPU from Intel or AMD. Meanwhile, Android and iOS devices, Apple computers, most microcontrollers, some Windows laptops, and some servers have ARM processors based on intellectual property licensed from ARM Limited. However, RISC-V provides an open alternative with anybody free to design and sell a RISC-V processor. Already, RISC-V has been widely adopted in microcontrollers and embedded systems. And, as I reported in last year's update, it is now possible to purchase RISC-V cloud server instances. RISC-V has a non-profit governing body called RISC-V International. This has over 4,500 members and is based in Switzerland. To help me make this video, I interviewed the CEO of RISC-V International, Andre Gallop. And, I'll be including some clips from our conversation.

RISC-V Progress

The last 12 months have been an exciting time for RISC-V. In September 2025, the SHD Group reported that RISC-V will reach 33. 7% market penetration by 2031, up from 2. 5% in 2021. SHD also predicted that by 2031, over 35 billion shipped SOCs will have a RISC-V core. These are, of course, just predictions, but there is no doubt that RISC-V adoption is growing rapidly, especially in the IoT and embedded processor marketplace. We've also had two very significant acquisitions. Firstly, in October 2025, Facebook owner Meta acquired Rivos, a startup founded in 2021 that developed RISC-V server processors and AI accelerators. Meta has been developing its own RISC-V processors and AI accelerators for several years, and so its acquisition of Rivos bolstered its internal RISC-V chip development, and makes it more likely that Meta will increasingly adopt RISC-V silicon. Secondly, in December 2025, Qualcomm acquired Ventana Micro Systems. As I covered in previous RISC-V updates, Ventana had developed a RISC-V server processor platform called Veyron. According to Qualcomm, its acquisition of Ventana marked a pivotal step in its journey to deliver industry-leading RISC-V based CPU technology. And it also shook the market. Indeed, when Qualcomm's purchase of Ventana was announced, it triggered the value of shares in ARM to fall, initially by nearly 10%. Back with RISC-V International, in January 2026, it released its first annual report. This can be freely downloaded and is a welcome initiative that I'll link in the video description. Back in October 2025, RISC-V International was also recognized by the ISO/IEC Joint Technical Committee as a submitter of publicly available specifications or PAS. This means that RISC-V can start the journey to become an ISO standard, which would provide an ever more solid foundation for the rising ISA.

RISC-V in Automotive

Automotive is a significant area of RISC-V application. In part, this is due to a shift towards software-defined vehicles or SDVs with a location-based zonal architecture. Here, multiple electronic control units or ECUs that control particular electrical components are connected to zonal controllers that manage specific physical areas of the vehicle. And these zonal controllers are then connected to a central compute unit. Compared to a traditional centralized architecture, this reduces the amount of wiring required in a vehicle as fewer sensors and actuators need to be directly connected to central compute. And with this context noted, I asked Andre Gallo why automotive is a key sector for RISC-V. Um on the technical side, um because RISC-V as a single ISA scales from the ECU to the zonal controller, to the AI accelerators, uh and to the central compute as a single ISA, as a single programming model. Then, of course, thanks to the modular architecture of RISC-V, you can scale down to a 32-bit RISC-V implementation for the ECU uh or a more powerful 64-bit for the zone controller with AI capabilities or central compute with all the security isolation extensions that allow you to run safety critical alongside rich operating systems. So, on the technical side, instead of having multiple different architectures depending on the blocks in the automotive and especially in the software-defined vehicle architecture, risk 5 is can be the single one scaling across from tiny CU to the central compute. Um in addition, of course, there is an element of um I would say uh risk 5 enables the multi-supplier strategy. Uh every OEM or every car maker can rely on multiple semiconductors providing risk 5 automotive grade parts. And every semiconductor can rely on multiple IP vendors. And every IP vendor, they have the confidence the the licensing terms, the creative commons that we use for our specifications, the fact that risk 5 is an open standard, open industry standard. It all means that everybody, wherever they are in this supply chain in the automotive industry, everyone has multiple suppliers that they can build on. So, risk 5 brings you these independence from a single vendor lock-in. It allows you to it brings you the confidence that you can build your road map for your company.

RISC-V & AI

RISC-V is already being used for AI. As noted earlier, Meta is a notable pioneer and uses RISC-V cores in its custom MTIA or Meta Training and Inference Accelerator AI chips. The first these was announced in May 2023 and in March 2026, Meta reported on the development of further MTIA chips that will help it to deliver AI experiences for billions of users. Many other companies are also developing RISC-V AI products. Not least, in September 2025, SiFive launched its second-generation intelligence family of licensable RISC-V processor designs which span an application range from edge AI to the data center. Other RISC-V AI pioneers include SemiDynamics, a European company who design RISC-V AI processors, and Esperanto who offer their RISC-V based Esperanto generative AI appliance. Google's latest Coral NPU, announced in October 2025, is also RISC-V based. And so, against this background of accelerating development, I asked Andre Gallop why RISC-V and AI appear to be a natural match. We have always said that RISC-V is AI native. Uh this is because the V in the name in RISC-V, yes, it's the Roman cardinal number for fifth generation coming from the Berkeley uh first RISC initiative, of course. But we also play with the fact that V stands for vectors, and RISC-V has had the most flexible vector implementation since the very beginning. Um So, RISC-V in AI can play multiple roles. It can be the controller of AI processing units. But it can also be the main processing unit thanks to the vector extensions and the upcoming matrix extensions. And it can also be the single compute unit that runs both the control software, the framework, the AI framework, and the processing itself. When you run the same code and you leverage vector extensions and soon the matrix extensions, it means that you will not need any DMA operations or mem copies or duplicating or moving data across the control and the NPU. So, you mem copies or DMA, they mean late they imply latency and power consumption. So, this is all saving. And so, having these extensions in RISC-V means that you can build a platform that does it all. So, RISC-V in AI is providing all the options and then depending on your design, you can find the right sweet spot.

RVA23 Silicon

Over the past 12 months on this channel, the new RISC-V development boards we've looked at have been these: the Orange Pi RV2 and the StarFive VisionFive 2 Light. And these are both nice RISC-V development boards. But, really over the past 12 months, we've all been waiting for new hardware based on the RVA23 RISC-V profile. This was ratified in October 2024 and sets a standard for binary compatible RISC-V processors that will be able to run the same software. Inevitably, there's been a gap between RVA23 being ratified and new hardware becoming available. But, the wait is just about over. And I, of course, asked Andre what is the significance of RVA23? It sets the baseline for modern application processors and it brings a binary compatibility at the application level for the operating systems. Um in a vertically integrated fully owned solution where you have uh you know the famous term of spaghetti code, uh you can also have your custom handcrafted RISC-V solution for your custom application and then you just own everything and carry the total cost of ownership. But when it comes to running an operating system, modern virtual operating system like uh a Canonical Ubuntu or Red Hat RHEL Enterprise Linux. Um you cannot do the port every time for every different RISC-V uh flavor. So, the RVA23 sets the baseline for this. Uh Canonical has been very vocal since the beginning. Uh Google Android uh praised uh the RVA23 immediately. Uh RHEL Red Hat announced a RHEL preview at the last Red Hat Summit last year. Uh and Nvidia announced plans to port CUDA to RISC-V using the RVA23 as the baseline. So, this means that every uh operating system vendor, software vendor, targets the RVA23 as the single build target. And then it runs on all the semiconductor implementation, all the designs that are compliant to the RVA23. And we see so many coming up. SpaceMeet 3 is available. Akiana announced their tapeout last January. Thenstor and Ascalon CPU is announced as well. So, there are so many coming out from all the players. So, this is really the year of the RVA23 silicon. Of the processors Andre just mentioned, for many enthusiasts, the most exciting is the SpaceMit K3. This has eight SpaceMit X100 CPU cores clocked at up to 2. 4 GHz and Imagination BX M4-64 MC1 GPU, eight A100 AI cores, and can deliver 60 TOPS of general AI compute power. SpaceBix X100 cores are claimed to outperform an ARM A76 in some tests. So, the octa-core K3 should offer decent performance. The K3 is intended to be used in AI smart home devices, conferencing solutions, content creation tools, and retail systems. However, it's also the SOC in new development boards, including the Milk-V Jupiter 2. This has up to 32 GB of RAM, up to 256 GB of UFS flash storage, and a four-lane PCIe 3. 0 M. 2 slot for an NVMe SSD. The Milk-V Jupiter 2 is expected to ship sometime in April 2026, and I hope to test one out on the channel very soon. You may also be interested to know that other K3 hardware includes the for the Framework laptop. Several pioneers have announced RVA23 compliant processors intended for cloud server applications. For example, Tenstorrent's Ascalon X RVA23 core is intended to compete with ARM Neoverse 2 and Neoverse 3 data center cores. A development board called Atlantis with eight Ascalon X cores has been reported for release in the second half of 2026. Also targeting the data center is Alibaba's chip division T-Head, which in March 2026 announced a design for the Xante C950. Unfortunately, I cannot access the English language version of its product page, but have managed to find a copy of its data sheet, which makes it clear that the C950 is a server-oriented processor. However, it should be noted that right now, like many RISC-V processors, the C950 is intellectual property only, or in other words, the design for a chip that has yet to be realized in silicon. Nevertheless, we are surely now on route to a time when many options will exist for data center servers to have a RISC-V processor.

RISC-V & Linux

To catalyze RISC-V software development, a project called RISE, standing for the RISC-V software ecosystem, is an industry initiative to accelerate the development of open-source RISC-V software. Premium members, including Nvidia, Red Hat, and Canonical, and indeed Linux support for RISC-V more generally is developing rapidly. Not least, Canonical has for several years been a strong supporter, and I've often run Ubuntu on RISC-V development boards on this channel. And Ubuntu 26. 04, which I'll review in the next video, is the first LTS release to support RVA23 compliant RISC-V hardware. As Andre highlighted, in May 2025, Red Hat announced a preview of Red Hat Enterprise Linux. In August 2025, Debian 13 was also released with RISC-V support. Other distros now offering some level of support for RISC-V include Fedora, openSUSE, and Arch Linux. In addition, we also have Bi-amp OS, which is a customized version of Ubuntu specifically optimized to run on risk-five hardware. Whilst these distros offer increasing opportunities for server and desktop risk-five computing, the next support is also needed for embedded hardware. To this end, in May 2025, risk-five international partnered with the Rise project to upgrade to a platinum membership of the Yocto project. This helps developers to create custom embedded Linux-based systems, and the new strategic alignment formalized the Yocto support for risk-five. To be specific, from Yocto 5. 3, risk-five is fully supported, which is excellent news for embedded developers.

Exciting Times

RISC-V is on the rise, and Andre Galloways' enthusiasm for it, the CEO of RISC-V International, is obvious. And in that context, I wanted to share with you the end of our conversation. Finally, is there anything I haven't asked you about that you'd like to tell us about? Um one thing you were um mentioning enthusiasm. Um when I got on the job, or actually during the interview process, I did all the I uh I went through the uh RISC-V multiple RISC-V courses, and I got the certifications. I wanted to show that I was really investing to get into RISC-V. My favorite one is design your RISC-V CPU core. It's a free course on the website, and that's mind-blowing. I think that every software engineer should take that course on how to design a simple RISC-V hardware core. A software engineer designing a hardware core. I loved it. I think every software engineer would love it as well. Hardware engineers may feel that it's basic, of course. But the fact that in a single browser window you have everything to design to have a hardware design, have the waveform analyzer, everything. It's fantastic. And these days we're running a community challenge with the Technical University of Graz in Austria. We have more than 700 students who registered. And together with Professor Tobias Schipflinger, they are learning how to design a risk five core. So this learning aspect of the risk five ecosystem is so exciting. And I really want to call it out because it's a huge effort by everybody involved. Well, that course sounds amazing. I can feel your enthusiasm for it. And I will of course put a link to that course in the video description. But now that's it for another video. If you've enjoyed what you've seen here, please press that like button. If you haven't subscribed, please subscribe. And I hope to talk to you again very soon.

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